Clock signal generating circuit and data output apparatus using the same

ABSTRACT

A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal.

TECHNICAL FIELD

The present disclosure relates to a data output apparatus and, moreparticularly, to a clock signal generating circuit capable ofcontrolling data output timing based on a fuse cutting.

BACKGROUND

Recently, the main issue of semiconductor memory devices is shifted froma degree of integration to an operating speed. Accordingly, high-speedsynchronous DRAMs such as a DDR SDRAM (Double Data Rate SynchronousDRAM) and a RAMBUS DRAM are focused on high-speed data processing units.

The high-speed synchronous DRAMs are memory devices in which data areprocessed in synchronization with an external clock signal and thisoperation mechanism is a mainstream approach in the mass production ofDRAM devices. The accesses for data input/output operation of the SDRAMsare carried out periodically in synchronization with a rising edge of anexternal clock signal. However, in the DDR SDRAM, the data input/outputoperation are periodically carried out twice in synchronization withrising and falling edges, respectively, of the external clock signalusing an internal DLL (Delay Locked Loop) circuit. That is, the DDRSDRAM is twice as fast as the SDRAM. Therefore, a high-speedsemiconductor memory device such as the DDR SDRAM produces a clocksignal (hereinafter, referred to as “rising clock signal rclk”) which isenabled in response to a rising edge time of the external clock signaland another clock signal (hereinafter, referred to as “falling clocksignal fclk”) which is enabled in response to a falling edge time of theexternal clock signal.

FIG. 1 is a circuit diagram illustrating a clock signal generatingcircuit by the conventional technology.

Referring to FIG. 1, the clock signal generating circuit of aconventional DDR SDRAM includes first and second clock signal generators100 and 110. The first clock signal generator 100 includes a pair ofinverters IV11 and IV12 for buffering an external clock signal ECLK, adelayer 101 for delaying an output signal of a node nd11 for apredetermine time, an inverter IV13 for inverting an output signal ofthe delayer 101, a logic circuit having a NAND gate ND11 for performinga NAND operation of the output signal of the node nd11 and an outputsignal of the inverter IV13, and an inverter IV14. The second clocksignal generator 110 includes a transfer gate T11 for transferring theexternal clock signal ECLK, an inverter IV15 for inverting an outputsignal of the transfer gate T11, a delayer 111 for delaying an outputsignal of a node nd12 for a predetermine time, an inverter IV16 forinverting an output signal of the delayer 111, and a logic circuithaving a NAND gate ND12 for performing a NAND operation of the outputsignal of the node nd12 and an output signal of the inverter IV16, andan inverter IV17

This configured clock signal generating circuit produces both a risingclock signal rclk having a predetermined pulse width in synchronizationwith a rising edge of the external clock signal ECLK and a falling clocksignal fclk having a predetermined pulse width in synchronization with afalling edge of the external clock signal ECLK. At a read operation,data are outputted in synchronization with the rising clock signal rclkas well as the falling clock signal fclk.

However, the rising and falling clock signals rclk and fclk of theconventional clock signal generating circuit can be outputted faster orlater under the influence of PVT (Process, Voltage and Temperature)fluctuation. For instance, as shown in FIG. 2, in a case that a MOStransistor has a fast operating characteristic according to amanufacturing process, data which are issued in synchronization with therising and falling clock signal rclk and fclk can be outputted fasterthan a predetermined data output section (more particularly, secondrising edge of the external clock signal ECLK).

SUMMARY

The present disclosure is directed to providing a semiconductor memorydevice having a clock signal generating circuit which is capable ofcontrolling a data output in compliance with PVT fluctuation bycontrolling an output timing of rising and falling clock signal based onfuse cutting.

According to an aspect of the present disclosure, there is provided asemiconductor memory device having a clock signal generating circuit togenerate an internal clock signal using an external clock signal from anexternal circuit, the clock signal generating circuit comprising a fuseunit for generating first and second fuse signals based on fuse cuttingof fuses, a control signal generating unit for generating first andsecond control signals in response to the fuse signals, a clock signaldelaying unit for generating a delayed clock signal by delaying theexternal clock signal by a delay section in accordance with the controlsignals, and a clock generating unit for generating a first internalclock signal in synchronization with a rising edge of the delayed clocksignal and for generating a second internal clock signal insynchronization with a falling edge of the delayed clock signal.

The fuse unit includes a pull-up device coupled between a power supplyterminal and a first node for performing a pull-up operation in responseto a ground voltage level, a first fuse coupled to the first node forgenerating the first fuse signal, and a second fuse coupled to the firstnode for generating the second fuse signal.

The control signal generating unit includes a first control signalgenerating unit including a first latch unit to perform a latchoperation in response to the first fuse signal and a first buffer tobuffer an output signal of the first latch unit, and a second controlsignal generating unit including a second latch unit to perform a latchoperation in response to the second fuse signal and a second buffer tobuffer an output signal of the second latch unit.

The first control signal generating unit has a pull-down element forperforming a pull-down operation at an input terminal of the firstcontrol signal generating unit in response to a reset signal.

The first latch unit includes an inverter for inverting a signal on aninput terminal of the first control signal generating unit, and apull-down element for performing a pull-down operation at the inputterminal of the first control signal generating unit in response to anoutput signal of the inverter.

The second control signal generating unit has a pull-down element forperforming a pull-down operation at an input terminal of the secondcontrol signal generating unit in response to a reset signal.

The second latch unit includes an inverter for inverting a signal on aninput terminal of the second control signal generating unit, and apull-down element for performing a pull-down operation at the inputterminal of the second control signal generating unit in response to anoutput signal of the inverter.

The clock signal delaying unit includes a first delayer for delaying theexternal clock signal by a first section in response to the first andsecond control signals, a second delayer for delaying the external clocksignal by a second section in response to the first control signal, anda logic unit for performing a logic operation of output signals of thefirst and second delayers.

The first delayer includes a first logic unit for performing a logicoperation of the first and second control signals, and a second logicunit for delaying the external clock signal in response to an outputsignal of the first logic unit

The second delayer includes a delay element for delaying the externalclock signal, and a buffer for buffering an output signal of the delayelement in response to the first control signal.

The clock generating unit includes a first internal clock generatingunit for generating the first internal clock signal with a first pulsewidth in synchronization with the rising edge of the delayed clocksignal, and a second internal clock generating unit for generating thesecond internal clock signal with a second pulse width insynchronization with the falling edge of the delayed clock signal.

The first internal clock generating unit includes a buffer for bufferingthe delayed clock signal, a delay element for delaying an output signalof the buffer by the first pulse width, and a logic unit for performinga logic operation of the output signal of the buffer and an outputsignal of the delay element.

The first internal clock generating unit includes a transfer gate fortransferring the delayed clock signal, a buffer for inverting an outputsignal of the transfer gate, a delay element for delaying an outputsignal of the buffer, and a logic unit for performing a logic operationof the output signal of the buffer and an output signal of the delayelement.

According to another aspect of the present disclosure, there is provideda semiconductor memory device having a data output apparatus to outputdata in synchronization with internal clock signals, the data outputapparatus comprising a clock signal generating circuit for generatingthe internal clock signals using an external clock signal, a data latchfor synchronizing the data from a memory core with the internal clocksignals, and an output driver for driving the data latch to output thedata to a DQ pad.

The clock signal generating circuit includes a fuse unit for generatingfirst and second fuse signals based on fuse cutting of fuses, a controlsignal generating unit for generating first and second control signalsin response to the fuse signals, a clock signal delaying unit forgenerating a delayed clock signal by delaying the external clock signalby a delay section specified by the control signals, and a clockgenerating unit for generating a first internal clock signal insynchronization with a rising edge of the delayed clock signal and forgenerating a second internal clock signal in synchronization with afalling edge of the delayed clock signal.

The fuse unit includes a pull-up device coupled between a power supplyterminal and a first node for performing a pull-up operation in responseto a ground voltage level, a first fuse coupled to the first node forgenerating the first fuse signal, and a second fuse coupled to the firstnode for generating the second fuse signal.

The control signal generating unit includes a first control signalgenerating unit for generating the first control signal, having a firstlatch unit to perform a latch operation in response to the first fusesignal and a first buffer to buffer an output signal of the first latchunit, and a second control signal generating unit for generating thesecond control signal, having a second latch unit to perform a latchoperation in response to the second fuse signal and a second buffer tobuffer an output signal of the second latch unit.

The clock signal delaying unit includes a first delayer for delaying theexternal clock signal by a first section in response to the first andsecond control signals, a second delayer for delaying the external clocksignal by a second section in response to the first control signal, anda logic unit for performing a logic operation of output signals of thefirst and second delayers.

The first delayer includes a first logic unit for performing a logicoperation of the first and second control signal, and a second logicunit for delaying the external clock signal in response to an outputsignal of the first logic unit.

The second delayer includes a delay element for delaying the externalclock signal, and a buffer for buffering an output signal of the delayelement in response to the first control signal.

The clock generating unit includes a first internal clock generatingunit for generating a first internal clock signal with a first pulsewidth in synchronization with the rising edge of the delayed clocksignal, and a second internal clock generating unit for generating asecond internal clock signal with a second pulse width insynchronization with the falling edge of the delayed clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of thesubject matter of the present disclosure can be more clearly understoodfrom the following detailed description taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a circuit diagram illustrating a clock signal generatingcircuit of a conventional DDR SDRAM;

FIG. 2 is a timing chart illustrating an operation of the clock signalgenerating circuit in FIG. 1;

FIG. 3 is a schematic diagram illustrating a data output apparatusaccording to an specific embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a clock signal generatingcircuit included in the data output apparatus in FIG. 3;

FIG. 5 is a circuit diagram illustrating a fuse unit included in clocksignal generating circuit of FIG. 4;

FIG. 6 is a circuit diagram illustrating a control signal generatingunit included in the clock signal generating circuit of FIG. 4;

FIG. 7 is a circuit diagram illustrating a clock signal delaying unitincluded in the clock signal generating circuit of FIG. 4;

FIG. 8 is a circuit diagram illustrating a clock generating unitincluded in the clock signal generating circuit of FIG. 4; and

FIG. 9 is a timing chart illustrating an operation of the clock signalgenerating circuit of FIG. 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the present invention will be described in detail throughexamples and exemplary embodiments. The examples and exemplaryembodiments merely exemplify the present invention, and the scope of thepresent disclosure and the appended claims is not limited by them.

First, referring to FIG. 3, a data output apparatus according to thepresent invention includes a clock signal generating unit 2, a DRAM core4, a data latch unit 6, a driver 8 and a DQ pad 10.

The clock signal generating unit 2 produces rising and falling clocksignals rclk and fclk, which have a predetermined pulse width, insynchronization with rising and falling edges of an external clocksignal ECLK. At this time, the rising and falling clock signals rclk andfclk are timing controlled based on fuse cutting.

More concretely, referring to FIG. 4, the clock signal generating unit 2according to the exemplary embodiment of FIG. 4 includes a fuse unit 20,a control signal generating unit 22, a clock signal delaying unit 24 anda clock generating unit 26.

The fuse unit 20, as shown in FIG. 5, includes a PMOS transistor PM21for performing a pull-up operation at a node nd21, a first fuse F1connected to the node nd21 for generating a first fuse signal FUSE1 anda second fuse F2 connected to the node nd21 for generating a second fusesignal FUSE2. At this time, the fuse is made of a conducting layer suchas a polysilicon layer, aluminum layer or a tungsten layer.

Referring to FIG. 6, the control signal generating unit 22 includes afirst control signal generating unit 220 for generating a first controlsignal fout1 in response to the first fuse signal FUSE1 and a secondcontrol signal generating unit 222 for generating a second controlsignal fout2 in response to the second fuse signal FUSE2.

The first control signal generating unit 220 includes an NMOS transistorNM21 for performing a pull-down operation at a node nd22 in response toa reset signal Reset, a latch unit 2200 having an inverter IV21 and anNMOS transistor NM22 in order to perform a latch operation in responseto an output signal from the node nd22, and a buffer (two inverters IV22and IV23) for buffering an output signal of the latch unit 2200. Here,the reset signal Reset is a signal which is transited from a highvoltage level to a low voltage level after a power supply voltage VCCgoes to a predetermined voltage level.

The second control signal generating unit 222 includes an NMOStransistor NM23 for performing a pull-down operation at a node nd24 inresponse to the reset signal Reset, a latch unit 2220 having an inverterIV24 and an NMOS transistor NM24 in order to perform a latch operationin response to an output signal from the node nd24, and a buffer (twoinverters IV25 and IV26) for buffering an output signal of the latchunit 2220.

The clock signal delaying unit 24, as shown in FIG. 7, includes a firstdelayer 240 for delaying the external clock signal ECLK for apredetermined time in response to the first and second control signalsfout1 and fout2, a second delayer 242 for delaying the external clocksignal ECLK for a predetermined time in response to the first controlsignal fout1, a third delayer 244 for delaying the external clock signalECLK for a predetermined time in response to the second control signalfout2, and a NAND gate ND24 configured to receive output signals of thefirst to third delayers 240 to 244 and generate a delayed clock signalECLKD by performing an OR operation of the received output signals.

The first delayer 240 includes a NOR gate NR21 for NORing the first andsecond control signals fout1 and fout2, an inverter IV32 for invertingan inverted signal of the external clock signal ECLK, and a NAND gateND21 for NANDing output signals of the NOR gate NOR21 and the inverterIV32.

The second delayer 242 includes an inverter IV33 for inverting theinverted signal of the external clock signal ECLK, a delay element 2401for delaying an output signal of the inverter IV33 for a predeterminedtime, and a NAND gate ND22 for NANDing an output signal of the delayelement 2401 and the first control signal fout1.

The third delayer 244 includes an inverter IV34 for inverting theinverted signal of the external clock signal ECLK, a delay element 2402for delaying an output signal of the inverter IV34 for a predeterminedtime, and a NAND gate ND23 for NANDing an output signal of the delayelement 2402 and the second control signal fout2. Preferably, the delaytime which is taken by the delay element 2402 of the third delayer 244is longer than that which is taken by the delay element 2401 of thesecond delayer 242.

Referring to FIG. 8, the clock generating unit 26 includes a risingclock signal generating unit 260 and a falling clock signal generatingunit 262.

The rising clock signal generating unit 260 includes a buffer 2600 forbuffering the delayed clock signal ECLKD, a delay element 2602 fordelaying an output signal of the buffer 2600 for a predetermined time,an inverter IV43 for inverting an output signal of the delay element2602, and a logic unit 2604 for ANDing the output signal of the buffer2600 and an output signal of the inverter IV43.

The falling clock signal generating unit 262 includes a transfer gateT21 for transferring the delayed clock signal ECLKD, an inverter IV45for inverting an output signal of the transfer gate T21, a delay element2620 for delaying an output signal of the inverter IV45 for apredetermined time, an inverter IV46 for inverting an output signal ofthe delay element 2620, and a logic unit 2622 for ANDing the outputsignals of the inverter IV46 and the inverter IV45.

The data latch unit 6 outputs the data, which are outputted from theDRAM core 4, in synchronization with the rising clock signal rclk andthe falling clock signal fclk.

The driver 8 drives the data latch 6 to output the data through the DQpad 10.

In the data output apparatus according to the exemplary embodiment ofthe present invention, the clock signal generating unit 2 produces therising clock signal rclk and the falling clock signal fclk using thereceived external clock signal ECLK. At this time, the timing of therising clock signal rclk and the falling clock signal fclk is controlledbased on the fuse cutting.

More concretely, the fuse unit 20 produces the first fuse signal FUSE1and the second fuse signal FUSE2 based on the cutting of the first fuseF1 and the second fuse F2. For, example, in a case that all of the firstfuse F1 and the second fuse F2 are not cut, the first and second fusesignals FUSE1 and FUSE2 are generated at a high level. In a case thatonly the first fuse F1 is cut, the first fuse signal FUSE1 is generatedat a low level and, in a case that only the second fuse F2 is cut, thesecond fuse signal FUSE2 is generated at a low level. At this time, itshould be noted that the fuse cutting is set up so as not to cut all ofthe first fuse F1 and the second fuse F2.

The control signal generating unit 22 produces the first control signalfout1 and the second control signal fout2 using the received first andsecond fuse signals FUSE1 and FUSE2. At this time, the voltage levels onthe nodes nd22 and nd24 are initialized by the reset signal Reset sothat the power supply voltage VCC goes to a predetermined voltage leveland the nodes nd22 and nd24 are at a low voltage level.

After the nodes nd22 and nd24 are at a predetermined low voltage level,the first control signal fout1 and the second control signal fout2 whichare respectively generated in response to the first and second fusesignals FUSE1 and FUSE2 that are generated by the fuse cutting of thefirst and second fuse F1 and F2 in the fuse unit 20 are shown in Table 1below.

TABLE 1 F1 F2 FUSE1 FUSE2 fout1 fout2 no no H H L L cut cut cut no L H HL cut no cut H L L H cut cut cut L L no used

The clock signal delaying unit 24 produces the delayed clock signalECLKD by delaying the external clock signal ECLK based on thecombination of the first and second control signals fout1 and fout2.That is, in a case that the first and second fuses F1 and F2 are notcut, the NOR gate NR21 outputs a high level signal and the NAND gatesND22 and ND23 output a high level signal because the first and secondcontrol signal fout1 and fout2 are generated at a low level. As aresult, the NAND gates ND21 and ND24 serve as inverters. Accordingly,the external clock signal ECLK, which is delayed by the inverters IV31and IV32 and the NAND gates ND21 and ND24, is outputted as the delayedclock signal ECLKD.

In a case that only the first fuse F1 is cut, the NAND gates ND21 andND23 output high level signals because the first control signal fout1 isgenerated at a high level and the second control signal fout2 isgenerated at a low level. As a result, the NAND gates ND22 and ND24serve as inverters. Accordingly, the external clock signal ECLK, whichis delayed by the inverters IV31 and IV33, the delay element 2401 andthe NAND gates ND22 and ND24, is outputted as the delayed clock signalECLKD.

Similarly, in a case that only the second fuse F2 is cut, the externalclock signal ECLK, which is delayed by the inverters IV31 and IV34, thedelay element 2402 and the NAND gates ND23 and ND24, is outputted as thedelayed clock signal ECLKD.

As mentioned above, the clock signal generating circuit 2 according tothe exemplary embodiment of the present invention outputs the delayedclock signal ECLKD by delaying the external clock signal ECLK throughdifferent delay sections based on the fuse cutting of the fuse F1 andF2. At this time, since the delay time of the delay element 2402included in the third delayer 244 is longer than that of the delayelement 2401 included in the second delayer 242 and the delay time ofthe delay element 2401 included in the second delayer 242 is longer thanthat of the inverter IV32 included in the first delayer 240, the delayedclock signal ECLKD has the smallest amount of delay when all of thefirst and second fuses F1 and F2 are not cut and has the largest amountof delay when only the second fuse F2 is cut.

The clock generating unit 26 produces the rising clock signal rclk andthe falling clock signal fclk using the delayed clock signal ECLKD. Atthis time, the pulse width of the rising clock signal rclk and thefalling clock signal fclk can be determined based on the delay amount ofthe delay elements 2602 and 2620.

The data latch 6 outputs the data from the DRAM core 4 insynchronization with the rising clock signal rclk and the falling clocksignal fclk and the driver 8 drives the data latch 6 to output the datathrough the DQ pad 10.

The data output apparatus according to the exemplary embodiment of thepresent invention produces a delayed clock signal ECLKD, a delay amountof which is controlled based on the fuse cutting such that the dataoutput timing is controlled by the rising clock signal rclk and thefalling clock signal fclk which are generated based on the delaycontrolled clock signal ECLKD.

A timing of the rising clock signal rclk and the falling clock signalfclk, each of which has a predetermined delay section, and a timing ofthe data output section (second rising edge of the external clock signalECLK) through the DQ pad 10 are shown in FIG. 9.

In the present invention, the electrical characteristics of MOStransistors, which are included in the clock signal generating unit forgenerating the rising clock signal rclk and the falling clock signalfclk, are of typical process and the fuse cutting is set up so as not tocut all of the first fuse F1 and the second fuse F2.

Accordingly, when the first fuse F1 is cut, the timing of the risingclock signal rclk and the falling clock signal fclk can be delayed bythe delayed external clock signal ECLKD which is generated through thesecond delayer 242, a delay time of which is longer than that of thefirst delayer 240.

At this time, in a case that the rising clock signal rclk and thefalling clock signal fclk are fast in spite of the fuse cutting of firstfuse F1, the timing of the rising clock signal rclk and falling clocksignal fclk can be delayed by using the delayed external clock signalECLKD which is generated by the third delayer 244.

As apparent from the above, the clock signal generating unit accordingto the present invention can control the data output timing based on thePVT fluctuation by controlling the timing of the rising clock signalrclk and the falling clock signal fclk using fuse cutting.

While the present invention has been described with respect to examplesand exemplary embodiments, it will be apparent to those skilled in theart that various changes and modifications may be made without departingfrom the spirit and scope of this disclosure and the following claims.

This disclosure claims priority to Korean application number10-2007-0131313, filed on Dec. 14, 2007, the entire contents of whichare incorporated herein by reference.

1. A fuse unit for generating fuse signals based on fuse cutting offuses; a control signal generating unit for generating control signalsin response to the fuse signals; a clock signal delaying unit forgenerating a delayed clock signal by delaying the external clock signalby a delay section in accordance with the control signals; and a clockgenerating unit for generating a first internal clock signal insynchronization with a rising edge of the delayed clock signal and forgenerating a second internal clock signal in synchronization with afalling edge of the delayed clock signal.
 2. The semiconductor memorydevice of claim 1, wherein the fuse unit includes: a pull-up devicecoupled between a power supply terminal and a first node for performinga pull-up operation in response to a ground voltage level; a first fusecoupled to the first node for generating the first fuse signal; and asecond fuse coupled to the first node for generating the second fusesignal.
 3. The semiconductor memory device of claim 2, wherein thecontrol signal generating unit includes: a first control signalgenerating unit including a first latch unit to perform a latchoperation in response to the first fuse signal and a first buffer tobuffer an output signal of the first latch unit; and a second controlsignal generating unit including a second latch unit to perform a latchoperation in response to the second fuse signal and a second buffer tobuffer an output signal of the second latch unit.
 4. The semiconductormemory device of claim 3, wherein the first control signal generatingunit has a pull-down element for performing a pull-down operation at aninput terminal of the first control signal generating unit in responseto a reset signal.
 5. The semiconductor memory device of claim 3,wherein the first latch unit includes: an inverter for inverting asignal on an input terminal of the first control signal generating unit;and a pull-down element for performing a pull-down operation at theinput terminal of the first control signal generating unit in responseto an output signal of the inverter.
 6. The semiconductor memory deviceof claim 4, wherein the second control signal generating unit has apull-down element for performing a pull-down operation at an inputterminal of the second control signal generating unit in response to areset signal.
 7. The semiconductor memory device of claim 3, wherein thesecond latch unit includes: an inverter for inverting a signal on aninput terminal of the second control signal generating unit; and apull-down element for performing a pull-down operation at the inputterminal of the second control signal generating unit in response to anoutput signal of the inverter.
 8. The semiconductor memory device ofclaim 3, wherein the clock signal delaying unit includes: a firstdelayer for delaying the external clock signal by a first section inresponse to the first and second control signals; a second delayer fordelaying the external clock signal by a second section in response tothe first control signal; and a logic unit for performing a logicoperation of output signals of the first and second delayers.
 9. Thesemiconductor memory device of claim 8, wherein the first delayerincludes: a first logic unit for performing a logic operation of thefirst and second control signal; and a second logic unit for delayingthe external clock signal in response to an output signal of the firstlogic unit.
 10. The semiconductor memory device of claim 8, wherein thesecond delayer includes: a delay element for delaying the external clocksignal; and a buffer for buffering an output signal of the delay elementin response to the first control signal.
 11. The semiconductor memorydevice of claim 1, wherein the clock generating unit includes: a firstinternal clock generating unit for generating the first internal clocksignal with a first pulse width in synchronization with the rising edgeof the delayed clock signal; and a second internal clock generating unitfor generating the second internal clock signal with a second pulsewidth in synchronization with the falling edge of the delayed clocksignal.
 12. The semiconductor memory device of claim 11, wherein thefirst internal clock generating unit includes: a buffer for bufferingthe delayed clock signal; a delay element for delaying an output signalof the buffer by the first pulse width; and a logic unit for performinga logic operation of the output signal of the buffer and an outputsignal of the delay element.
 13. The semiconductor memory device ofclaim 11, wherein the first internal clock generating unit includes: atransfer gate for transferring the delayed clock signal; a buffer forinverting an output signal of the transfer gate; a delay element fordelaying an output signal of the buffer; and a logic unit for performinga logic operation of the output signal of the buffer and an outputsignal of the delay element.
 14. A clock signal generating circuit forgenerating the internal clock signals using an external clock signal; adata latch for synchronizing the data from a memory core with theinternal clock signals; and an output driver for driving the data latchto output the data to a DQ pad.
 15. The semiconductor memory device ofclaim 14, wherein the clock signal generating circuit includes: a fuseunit for generating first and second fuse signals based on fuse cuttingof fuses; a control signal generating unit for generating first andsecond control signals in response to the fuse signals; a clock signaldelaying unit for generating a delayed clock signal by delaying theexternal clock signal by a delay section in accordance with the controlsignals; and a clock generating unit for generating a first internalclock signal in synchronization with a rising edge of the delayed clocksignal and for generating a second internal clock signal insynchronization with a falling edge of the delayed clock signal.
 16. Thesemiconductor memory device of claim 15, wherein the fuse unit includes:a pull-up device coupled between a power supply terminal and a firstnode for performing a pull-up operation in response to a ground voltagelevel; a first fuse coupled to the first node for generating the firstfuse signal; and a second fuse coupled to the first node for generatingthe second fuse signal.
 17. The semiconductor memory device of claim 15,wherein the control signal generating unit includes: a first controlsignal generating unit for generating the first control signal, having afirst latch unit to perform a latch operation in response to the firstfuse signal and a first buffer to buffer an output signal of the firstlatch unit; and a second control signal generating unit for generatingthe second control signal, having a second latch unit to perform a latchoperation in response to the second fuse signal and a second buffer tobuffer an output signal of the second latch unit.
 18. The semiconductormemory device of claim 15, wherein the clock signal delaying unitincludes: a first delayer for delaying the external clock signal by afirst section in response to the first and second control signals; asecond delayer for delaying the external clock signal by a secondsection in response to the first control signal; and a logic unit forperforming a logic operation of output signals of the first and seconddelayers.
 19. The semiconductor memory device of claim 18, wherein thefirst delayer includes: a first logic unit for performing a logicoperation of the first and second control signal; and a second logicunit for delaying the external clock signal in response to an outputsignal of the first logic unit.
 20. The semiconductor memory device ofclaim 18, wherein the second delayer includes: a delay element fordelaying the external clock signal; and a buffer for buffering an outputsignal of the delay element in response to the first control signal. 21.The semiconductor memory device of claim 15, wherein the clockgenerating unit includes: a first internal clock generating unit forgenerating a first internal clock signal with a first pulse width insynchronization with the rising edge of the delayed clock signal; and asecond internal clock generating unit for generating a second internalclock signal with a second pulse width in synchronization with thefalling edge of the delayed clock signal.